1. Field of the Invention
This invention relates to the field of computer systems and, more particularly, to distributed hardware emulation environments.
2. Description of the Related Art
Generally, the development of components for an electronic system such as a computer system includes design verification of the components, which may be accomplished, for example, by simulation of models of the components, or by hardware emulation of the components. During design verification, the specified functions of each component may be tested and, when incorrect operation (a bug) is detected, the model or emulation circuitry of the component may be changed to generate correct operation. Once design verification is complete, the component may be fabricated. Since many of the bugs may have been detected in design verification, the component may be more likely to operate as specified and the number of revisions to hardware may be reduced. Simulation models are frequently described in a hardware description language (HDL) such as Verilog, VHDL, etc.
Originally, simulations of electronic systems were performed on a single computing system. However, as the electronic systems (and the components forming systems) have grown larger and more complex, single-system simulation has become less desirable. The speed of the simulation (in cycles of the electronic system per second) may be reduced due to the larger number of gates in the model which require evaluation. Additionally, the speed may be reduced as the size of the electronic system model and the computer code to perform the simulation may exceed the memory capacity of the single system. In some cases, the simulators may not be capable of simulating the entire model. As the speed of the simulation decreases, simulation throughput is reduced.
To address these issues, distributed simulation has become more common. Generally, a distributed simulation system includes two or more computer systems (i.e. nodes) simulating portions of an electronic system in parallel. Furthermore, each node must communicate with other nodes to transfer information between different simulated portions of the electronic system, i.e., to coordinate and/or synchronize steps of the distributed simulation. For example, a distributed simulation system may sample output signals from the portions of the system simulated by each node and communicate the corresponding signal values to other nodes. The received signal values are then driven as inputs to the models in those other nodes.
Hardware emulation has typically been performed using expensive, often proprietary emulation servers that may contain custom-built hardware emulation devices. Such emulation servers may, for example, be limited to using a maximum number of emulation devices such as field programmable gate arrays (FPGAs) that may be incorporated within the proprietary design of the emulation server. Hardware emulation for a given component may typically be accomplished faster than a software simulation for the same component. For large and complex designs, however, the total amount of design verification required may exceed the emulation capacity supported by an emulation server. A technique that allows flexible configuration of hardware emulation capacity (e.g., using inexpensive commodity hardware), and uses inter-node communication to coordinate distributed hardware emulation in a manner similar to the coordination techniques used in distributed software simulation, may therefore be desirable.